Design and implementation of a reversible central processing unit

Abstract

Reversible logic is an emerging technology. Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. Reversible computing spans computational models that are both forward and backward deterministic. Reversible logic circuits require some constant ancilla inputs to generate the required functions. It produces some unused outputs, called garbage outputs, to maintain the reversibility of a circuit. It is important to minimize the number of ancilla inputs, number of garbage outputs and quantum cost in the design of reversible circuits. Reversible logic has promising applications in emerging computing paradigm such as quantum computing, DNA computing, optical computing, quantum dot cellular automata etc. The central processing unit (CPU) is regarded as the brain of a computer. It is a piece of hardware that carries out the instructions needed to run a computer program. Processor speed determines the performance of a computer. It performs the basic arithmetical, logical, and input/output operations of a computer system. Advanced conventional processors have inherently higher power dissipation. The arithmetic logic unit of CPU performs simple arithmetic and logical operations and the control unit of CPU manages the various components of the computer. Power dissipation is the main constrain when it comes to portability. Reversible logic gates are designed as a method to reduce the energy dissipation of logic circuits based on Launder ′ s concept. Central processing unit designed using reversible logic have a significant contribution in low power computing. Launder proved that a reversible circuit produces less power than the irreversible circuit. Moreover, by using power optimization algorithm, the power consumption of a reversible circuit can be optimized than their existing reversible counterparts. For example, for a 64-bit comparator, the proposed circuit achieves the improvement of 55.67% in terms of power over the existing reversible one. Reversible circuit has some disadvantageous properties. It requires a large number of constant ancilla inputs. It also produces a large number of garbage outputs to maintain the reversibility which eventually increases the number of gates, area, power and delay. By using efficient design techniques and suitable algorithmsthe number of garbage outputs should be minimized. For example, for a 64-bit comparator, the proposed circuit achieves the improvement of 33.1% in terms of garbage outputs over the existing reversible one. As reversible computing is a new era in logic synthesis, the existing reversible central processing units have the lack of completeness. However, researchers proposed various basic components of reversible central processing unit. In this thesis, the basic elements of the reversible circuits are newly proposed or improved in terms of numbers of gates, garbage outputs, quantum cost and delay compared to the existing counterparts. The proposed reversible basic elements are further used to construct the complex circuits, such as memory circuits, arithmetic logic unit, control unit etc., in order to design a complete reversible central processing unit. The main contribution of this thesis is to design a new reversible central processing unit which is efficient in terms of numbers of gates, garbage outputs, quantum cost, ancilla inputs and delay. The reversible central processing unit is designed using novel modularization approach by presenting architecture of a logically reversible processor based on the Von Neumann architecture that can operate with very low power consumption, protection of power analysis attack and long span of life due to less heat dissipation. The organization and architecture of the proposed processor is designed from scratch. Algorithms are proposed to produce the components of the reversible processor and to calculate area and power consumption. The capabilities of the new processor is determined, the datapath layout is designed and the necessary logic is constructed to control the datapath. The computational complexity is considered to estimate the execution time of the algorithm. Existing component designs are compared with the proposed components and theorems are presented to prove the superiority of the proposed architecture. The comparative results show that the proposed circuit requires less power than the existing circuits in terms of numbers of gates, garbage outputs, quantum cost, area and power. For example, for a 64-bit comparator, the proposed design achieves the improvement of 66.6% in terms of number of gates, 33.1% in terms of garbage outputs, 27.6% in terms of quantum cost, 52.39% in terms of area and 55.67% in terms of power over the existing reversible counterpart. The proposed components are simulated and the simulation results verify the correctness of the proposed design. The proposed reversible central processing unit can make a significant contribution in the field of low power reversible computing and quantum computing.