Design and Implementation of Reversible Programmable Devices

Abstract

Reversible logic is a computing design, where the ideal implementation would produce zero entropy gain. This unique feature causes the prominent use of reversible computing. More integration capability and regular structure for synthesizing a large number of logic functions made programmable devices enthusiastic to use. In this thesis, we describe efficient design procedures of two programmable devices namely Programmable Logic Array (PLA) and Field Programmable Gate Array (FPGA) with reversible logic gate. In the first part of this thesis, we design the reversible Programmable Logic Array (RPLA). Here, we propose an efficient algorithm to design the RPLA with a newly proposed 3 × 3 reversible TB (Tara-Babu) gate, which can realize multioutput ESOP (Exclusive-OR Sum of Product) functions. We present a heuristic algorithm to sort and realize the product terms of ESOP functions to share the internal sub-products to reduce the number of gates in the proposed RPLA. Proposed algorithms make the RPLA more efficient with improvement of 9.83% in terms of the number of gates, 21.3% in terms of the number of garbage outputs and 14.75% in terms of quantum cost than the counter metrics of the existing RPLA averagely. Moreover, we compute the area requirement and the power consumption of the proposed RPLA. We also analyze the performances by using MCNC benchmark functions. In the last part of this thesis, we design the most significant part of a Field Programmable Gate Array, the Plessey Logic Block with reversible gate. On the way to design the proposed reversible Plessey Logic Block, we design each component such as reversible D-Latch, reversible Decoder, reversible Multiplexer, reversible Master-Slave Flip-Flop, and reversible RAM separately. The proposed design of the individual component is primarily made efficient in terms of the number of gates, garbage outputs, quantum cost, and delay. In addition, area and power are reduced to ensure the power efficiency of the circuits. Two 4 × 4 reversible gates, namely HNF (Hafiz-Naz-Flip-Flop) gate and HND (Hafiz-Naz-Decoder) gate are proposed to achieve the optimization goal. Moreover, proposed algorithms, lemmas and theorems certify the novelty of the proposed design. Compared to previous works, the proposed counter-parts of Reversible Plessey Logic Block require less number of gates, garbage outputs, quantum cost, and delay. Finally, the proposed Reversible Plessey (4 × 2) Logic Block is compared with existing designs. The Comparative results prove the efficacy and novelty of the proposed design showing improvement of 51.62% in terms of number of Transistor, 73.57% in terms of area requirement and 34.12% in terms of power consumption with respect to the corresponding metrics of the best existing design in the literature